模拟CMOS集成电路设计 第2版PDF|Epub|txt|kindle电子书版本网盘下载

模拟CMOS集成电路设计 第2版PDF格式电子书版下载

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1 Introduction to Analog Design1

1.1 Why Analog?1

1.1.1 Sensing and Processing Signals1

1.1.2 When Digital Signals Become Analog2

1.1.3 Analog Design Is in Great Demand3

1.1.4 Analog Design Challenges4

1.2 Why Integrated?4

1.3 Why CMOS?5

1.4 Why This Book?5

1.5 Levels of Abstraction5

2 Basic MOS Device Physics7

2.1 General Considerations8

2.1.1 MOSFET as a Switch8

2.1.2 MOSFET Structure8

2.1.3 MOS Symbols9

2.2 MOS I/V Characteristics10

2.2.1 Threshold Voltage10

2.2.2 Derivation of I/V Characteristics12

2.2.3 MOS Transconductance19

2.3 Second-Order Effects20

2.4 MOS Device Models26

2.4.1 MOS Device Layout26

2.4.2 MOS Device Capacitances27

2.4.3 MOS Small-Signal Model31

2.4.4 MOS SPICE models34

2.4.5 NMOS Versus PMOS Devices35

2.4.6 Long-Channel Versus Short-Channel Devices35

2.5 Appendix A: FinFETs36

2.6 Appendix B: Behavior of a MOS Device as a Capacitor37

3 Single-Stage Amplifiers45

3.1 Applications45

3.2 General Considerations45

3.3 Common-Source Stage47

3.3.1 Common-Source Stage with Resistive Load47

3.3.2 CS Stage with Diode-Connected Load52

3.3.3 CS Stage with Current-Source Load58

3.3.4 CS Stage with Active Load59

3.3.5 CS Stage with Triode Load60

3.3.6 CS Stage with Source Degeneration61

3.4 Source Follower68

3.5 Common-Gate Stage75

3.6 Cascode Stage82

3.6.1 Folded Cascode90

3.7 Choice of Device Models92

4 Differential Amplifiers100

4.1 Single-Ended and Differential Operation100

4.2 Basic Differential Pair103

4.2.1 Qualitative Analysis104

4.2.2 Quantitative Analysis106

4.2.3 Degenerated Differential Pair116

4.3 Common-Mode Response118

4.4 Differential Pair with MOS Loads123

4.5 Gilbert Cell126

5 Current Mirrors and Biasing Techniques134

5.1 Basic Current Mirrors134

5.2 Cascode Current Mirrors139

5.3 Active Current Mirrors146

5.3.1 Large-Signal Analysis149

5.3.2 Small-Signal Analysis152

5.3.3 Common-Mode Properties156

5.3.4 Other Properties of Five-Transistor OTA159

5.4 Biasing Techniques160

5.4.1 CS Biasing161

5.4.2 CG Biasing164

5.4.3 Source Follower Biasing165

5.4.4 Differential Pair Biasing166

6 Frequency Response of Amplifiers173

6.1 General Considerations173

6.1.1 Miller Effect174

6.1.2 Association of Poles with Nodes179

6.2 Common-Source Stage180

6.3 Source Followers188

6.4 Common-Gate Stage193

6.5 Cascode Stage196

6.6 Differential Pair198

6.6.1 Differential Pair with Passive Loads198

6.6.2 Differential Pair with Active Load201

6.7 Gain-Bandwidth Trade-Offs203

6.7.1 One-Pole Circuits204

6.7.2 Multi-Pole Circuits205

6.8 Appendix A: Extra Element Theorem206

6.9 Appendix B: Zero-Value Time Constant Method208

6.10 Appendix C: Dual of Miller's Theorem212

7 Noise219

7.1 Statistical Characteristics of Noise219

7.1.1 Noise Spectrum221

7.1.2 Amplitude Distribution224

7.1.3 Correlated and Uncorrelated Sources225

7.1.4 Signal-to-Noise Ratio226

7.1.5 Noise Analysis Procedure227

7.2 Types of Noise228

7.2.1 Thermal Noise228

7.2.2 Flicker Noise234

7.3 Representation of Noise in Circuits236

7.4 Noise in Single-Stage Amplifiers243

7.4.1 Common-Source Stage244

7.4.2 Common-Gate Stage249

7.4.3 Source Followers253

7.4.4 Cascode Stage254

7.5 Noise in Current Mirrors254

7.6 Noise in Differential Pairs256

7.7 Noise-Power Trade-Off263

7.8 Noise Bandwidth264

7.9 Problem of Input Noise Integration265

7.10 Appendix A: Problem of Noise Correlation265

8 Feedback274

8.1 General Considerations274

8.1.1 Properties of Feedback Circuits275

8.1.2 Types of Amplifiers282

8.1.3 Sense and Return Mechanisms284

8.2 Feedback Topologies286

8.2.1 Voltage-Voltage Feedback286

8.2.2 Current-Voltage Feedback291

8.2.3 Voltage-Current Feedback294

8.2.4 Current-Current Feedback297

8.3 Effect of Feedback on Noise298

8.4 Feedback Analysis Difficulties299

8.5 Effect of Loading303

8.5.1 Two-Port Network Models303

8.5.2 Loading in Voltage-Voltage Feedback304

8.5.3 Loading in Current-Voltage Feedback308

8.5.4 Loading in Voltage-Current Feedback310

8.5.5 Loading in Current-Current Feedback313

8.5.6 Summary of Loading Effects315

8.6 Bode's Analysis of Feedback Circuits315

8.6.1 Observations315

8.6.2 Interpretation of Coefficients317

8.6.3 Bode's Analysis320

8.6.4 Blackman'sImpedance Theorem325

8.7 Middlebrook's Method331

8.8 Loop Gain Calculation Issues332

8.8.1 Preliminary Concepts332

8.8.2 Difficulties with Return Ratio334

8.9 Alternative Interpretations of Bode's Method336

9 Operational Amplifiers344

9.1 General Considerations344

9.1.1 Performance Parameters344

9.2 One-Stage Op Amps349

9.2.1 Basic Topologies349

9.2.2 Design Procedure353

9.2.3 Linear Scaling354

9.2.4 Folded-Cascode Op Amps355

9.2.5 Folded-Cascode Properties358

9.2.6 Design Procedure359

9.3 Two-Stage Op Amps361

9.3.1 Design Procedure363

9.4 Gain Boosting364

9.4.1 Basic Idea364

9.4.2 Circuit Implementation368

9.4.3 Frequency Response371

9.5 Comparison373

9.6 Output Swing Calculations373

9.7 Common-Mode Feedback374

9.7.1 Basic Concepts374

9.7.2 CM Sensing Techniques377

9.7.3 CM Feedback Techniques380

9.7.4 CMFB in Two-Stage Op Amps386

9.8 Input Range Limitations388

9.9 Slew Rate390

9.10 High-Slew-Rate Op Amps397

9.10.1 One-Stage Op Amps397

9.10.2 Two-Stage Op Amps399

9.11 Power Supply Rejection400

9.12 Noise in Op Amps402

10 Stability and Frequency Compensation410

10.1 General Considerations410

10.2 Multipole Systems414

10.3 Phase Margin416

10.4 Basic Frequency Compensation420

10.5 Compensation of Two-Stage Op Amps426

10.6 Slewing in Two-Stage Op Amps433

10.7 Other Compensation Techniques436

10.8 Nyquist's Stability Criterion439

10.8.1 Motivation439

10.8.2 Basic Concepts440

10.8.3 Construction of Polar Plots442

10.8.4 Cauchy's Principle447

10.8.5 Nyquist's Method447

10.8.6 Systems with Poles at Origin450

10.8.7 Systems with Multiple 180° Crossings454

11 Nanometer Design Studies459

11.1 Transistor Design Considerations459

11.2 Deep-Submicron Effects460

11.3 Transconductance Scaling463

11.4 Transistor Design466

11.4.1 Design for Given ID and VDs，min466

11.4.2 Design for Given gm and ID469

11.4.3 Design for Given gm and VDs，min470

11.4.4 Design for a Given gm471

11.4.5 Choice of Channel Length472

11.5 Op Amp Design Examples472

11.5.1 Telescopic Op Amp473

11.5.2 Two-Stage Op Amp487

11.6 High-Speed Amplifier495

11.6.1 General Considerations496

11.6.2 Op Amp Design500

11.6.3 Closed-Loop Small-Signal Performance501

11.6.4 Op Amp Scaling502

11.6.5 Large-Signal Behavior505

11.7 Summary507

12 Bandgap References509

12.1 General Considerations509

12.2 Supply-Independent Biasing509

12.3 Temperature-Independent References513

12.3.1 Negative-TC Voltage513

12.3.2 Positive-TC Voltage514

12.3.3 Bandgap Reference515

12.4 PTAT Current Generation523

12.5 Constant-Gm Biasing524

12.6 Speed and Noise Issues525

12.7 Low-Voltage Bandgap References529

12.8 Case Study533

13 Introduction to Switched-Capacitor Circuits539

13.1 General Considerations539

13.2 Sampling Switches543

13.2.1 MOSFETS as Switches543

13.2.2 Speed Considerations547

13.2.3 Precision Considerations549

13.2.4 Charge Injection Cancellation553

13.3 Switched-Capacitor Amplifiers555

13.3.1 Unity-Gain Sampler/Buffer555

13.3.2 Noninverting Amplifier562

13.3.3 Precision Multiply-by-Two Circuit567

13.4 Switched-Capacitor Integrator568

13.5 Switched-Capacitor Common-Mode Feedback571

14 Nonlinearity and Mismatch576

14.1 Nonlinearity576

14.1.1 General Considerations576

14.1.2 Nonlinearity of Differential Circuits579

14.1.3 Effect of Negative Feedback on Nonlinearity581

14.1.4 Capacitor Nonlinearity583

14.1.5 Nonlinearity in Sampling Circuits584

14.1.6 Linearization Techniques585

14.2 Mismatch591

14.2.1 Effect of Mismatch593

14.2.2 Offset Cancellation Techniques598

14.2.3 Reduction of Noise by Offset Cancellation602

14.2.4 Alternative Definition of CMRR603

15 Layout and Packaging607

15.1 General Layout Considerations607

15.1.1 Design Rules608

15.1.2 Antenna Effect610

15.2 Analog Layout Techniques610

15.2.1 Multifinger Transistors611

15.2.2 Symmetty613

15.2.3 Shallow Trench Isolation Issues617

15.2.4 Well Proximity Effects618

15.2.5 Reference Distribution618

15.2.6 Passive Devices620

15.2.7 Interconnects627

15.2.8 Pads and ESD Protection631

15.3 Substrate Coupling634

15.4 Packaging638